Design of test architectures for VLSI devices

Abstract

Test architectures are implementation suggestions for ensuring good testability by means of a suitable selection, configuration and interlinking of easily testable modules. They supply models for automatic test preparation and thus offer a promising way of reducing the testing problems occurring in VLSI components. However, the tools and methods hitherto available for supporting their design and the test preparation coordinated with it are insufficient. The present work presents a new strategy for the design of test architectures and a conceptual approach to their associated test preparation. The test architecture is derived at the various abstraction levels while keeping pace with the top-down design of the chip and is supported by a hierarchical testability evaluation. In contrast to previous techniques, a knowledge of the function, structure and hierarchy of the circuit will be accessible to the generation of test patterns by means of procedures such as a hierachical value range analysis.