Design of Superscalar Processor with Multi-Bank Register File

Abstract

Recently, register files in highly parallel superscalar processors tend to have large chip areas and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the methods for solving these problems, we have proposed a multi-bank register file which realizes small area, high speed and low power consumption. We have proved the effectiveness of this method by simulation. We now show a detailed design of a superscalar processor with a multi-bank register file and its evaluation results. From the design by Verilog-HDL, the processor with the multi-bank register file improves register access speed by 49% at the cost of 28% more gates for register-access scheduling. These results verify that we have solved the problem of shortening the critical path around the register file in highly parallel processors.