Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications

Abstract

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06×/ 1.08×/ 1.36× shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03×/ 1.09×/ 1.12×/ 1.15×/ 1.17× shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33×/ 1.6×/ 2.4× higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13×/ 1.32×/ 1.37×/ 1.42×/ 1.5× higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31×/ 2.42×/ 2.55×/ 3.04× lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.