Design of Soft Edge Flip Flops for the Reduction of Power Delay Product in Linear Pipeline Circuits

Abstract

In VLSI Design Static Timing Analysis (STA) is carried out for timing closure of a design. Due to some process variations statistical analysis should also be carried out for accuracy. In this work, comparision between normal D-Flip Flop and Soft Edge Flip Flops(SEFF) is done. SEFFs are a type of Flip Flops created by modifying the conventional D-Flip Flops in order to create a transparency window. The aim of this work is to design a library of SEFFs so that the power and delay are reduced for various voltage and frequency settings under various scenarios by both deterministic and statistical delays. Power and delay analyses are carried on SEFF and conventional D-Flip Flop. This designed SEFF is utilized in a conventional Linear Pipeline to reduce the overall Power Delay product (PDP) of it. The simulations are carried out in Cadence Virtuoso for gpdk90nm and gpdk45nm technology libraries. It is observed that a power reduction of nearly 70 percent is observed from D-Flip Flop to SEFF (at 137.40ps transparency window width and 1.2V). A comparison between gpdk90nm and gpdk45nm is also done in this work.