Abstract
A silicon piezo-resistive smart pressure sensor is designed for implementation with a 0.6 /spl mu/m double poly double metal CMOS process. This smart sensor is composed of a diaphragm with piezoresistive resistors, Wheatstone bridge and circuitry composed of op-amp, A/D converter and UART. The relationship between the bridge output voltage and the mechanical stress due to pressure was studied by simulating the stress distribution on the diaphragm with the COSMOS-M package program. The CMOS op-amp circuit was designed with different transistor sizes to obtain the defined output characteristics and simulated with HSPICE. The A/D converter was designed using a neuron MOSFET structure and a sub-ranging method to minimize the chip area. The UART circuit was designed using VHDL source code and cell library by synthesizing with Synopsys, and the physical layout of the circuit is designed with Mentor tools. The temperature compensation and output-offset problem are to be studied further.
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