Design of single-ended SRAM with high test coverage and short test time

Chi-Feng Wu Chi-Feng Wu,Chua-Chin Wang Chua-Chin Wang,Chia-Hsiung Kao Chia-Hsiung Kao,Rain-Ted Hwang Rain-Ted Hwang

doi:10.1109/iscas.1998.706915

Design of single-ended SRAM with high test coverage and short test time

Chi-Feng Wu Chi-Feng Wu, Chua-Chin Wang Chua-Chin Wang + Show 2 more

https://doi.org/10.1109/iscas.1998.706915

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Publication Date: May 31, 1998

Affiliation: National Sun Yat-sen University

#Single-ended SRAM #High Test Coverage + Show 8 more

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Abstract

The advantages of low power dissipation and smaller chip area for single-ended SRAM are well known. In this paper we present the configuration and the test strategy of a single-ended six-transistor SRAM. The benefits of short test time, no retention test and high test coverage are verified. The goal of high quality control and short test time of full CMOS SRAM test can be achieved.

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