Design of single flux quantum cells for a 10-Nb-layer process

Abstract

We present design of single flux quantum (SFQ) cells for a 10-Nb-layer process which has been developed to fabricate SFQ VLSI circuits. The device fabricated by the process has a structure of an active layer on the top, two passive transmission line (PTL) layers in the middle, and a DC power (DCP) layer at the bottom. We have determined a unit cell size of 30 μm × 30 μm and a unit cell structure by taking accounts of the design rules and the experimental data on the PTLs. This cell size enables us to draw two PTLs of each PTL layer. PTL driver and receiver cells have a unit cell size, whereas a half unit cell with a size of 15 μm × 15 μm is used for PTL segments and vias. On the active layer, circuit parameters in analog simulation level are based on those of CONNECT cells, except for junction parameters with McCumber parameter β c of 2.0. Major cells including logic cells and PTL driver/receiver cells have been developed. We have designed a 2 × 2 switch on-chip test circuit using the cells and successfully tested them at high speed.