Design of Si and SiGe p-channel SOI MOSFET

Abstract

There is a great deal of interest in combining SOI and SiGe technologies. In this work we present a systematic study of scaling properties of n + and p + gate SOI Si and SiGe p-MOSFETs by using two-dimensional numerical simulation. It was found that for both Si and SiGe devices, n + gate is better suited for the design of fully depleted devices while for the design of partially depleted or near-fully depleted devices p + gate is a better choice. Overall, the n + gate is a better solution since we can design a device that is very low doped, fully depleted, satisfies all the design criteria, has small threshold voltage ( V TH) sensitivity to the silicon film thickness ( t Si) and sharp subthreshold slope. The SiGe device shows increase in linear transconductance of 24%, smaller increase in saturation transconductance, improved current drive and extended range of design options. Our results also indicate that reduction of the t Si is more effective in controlling the DIBL and SCE in low doped n + gate designs, than increase in doping. The n + gate design requires p + doping spike for threshold voltage adjustment. For the case of Si p + gate design, V TH can be easily adjusted by changing the doping level in the channel. Since the doping level used is relatively high this naturally leads to partially depleted devices in order to avoid large dependence of V TH on the t Si. However, a fully depleted device can be designed to have low dependence of V TH on the t Si. This is done by utilizing the t Si dependence of: (1) the total charge under the gate; and (2) source-body potential barrier. If the thickness is reduced, the first effect reduces while the second one increases the threshold voltage making the dependence of V TH on the thickness acceptable. The p + gate SiGe SOI p-MOSFET requires high body doping levels and exhibits large subthreshold slope and reduced transconductance.