Design of self-aligned 3.3-kV DMOSFET using tilted ion implantation

Abstract

In this paper, a simple self-aligned process for defining short channels in 3.3-kV SiC DMOSFETs is presented and designed using a TCAD simulation. The proposed process involves channel definition by Al ion implantation at a tilted angle through the source mask and eliminates the complicated hard mask etching process. The simulation results show that implantation of 1× 1013 /cm2 and 450 keV at a 30° tilt angle forms a self-aligned channel with a length of 0.65 μm and a sufficient blocking voltage. Assuming a mask alignment error, fluctuation of threshold voltages in a self-aligned device is estimated to be reduced to about one-third of that in a conventional device.