Design of Scalable Superconducting Quantum Circuits Using Flip-Chip Assembly

Abstract

We present design results of scalable superconducting quantum circuits using the flip-chip assembly. In order to achieve the longest relaxation time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{1}$</tex-math></inline-formula> ) of a qubit possible, gap between two chips in flip-chip assembly is determined to be 12 μm where low surface dielectric loss from two-level system (TLS) defects can be achieved while maintaining large readout coupling strength between two chips in the flip-chip assembly. Superconducting transmon qubit design is then optimized to have a target anharmonicity of 200 MHz and to have the longer <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{1}$</tex-math></inline-formula> in consideration of surface energy participation ratios of TLS defects within the compact footprint. To achieve strong coupling strength but low qubit to qubit crosstalk (ZZ) for fast and high fidelity multi-qubit gates, direct coupler and compact multi-path coupler designs for coupling qubits are compared by numerically solving Hamiltonian of the coupled two qubits. Monte-Carlo simulation results on the yield rate of the extended circuits indicate that low manufacturing errors are required.