Design of RSA processor for concurrent cryptographic transformations

Abstract

The performance of RSA depends strongly on the competent implementation of modular multiplication and modular exponentiation. Performance can be improved in three ways: (i) by reducing the frequency of modular multiplications; (ii) by reducing the time required to evaluate modular multiplication; (iii) by increasing the RSA cores. This work proposes enhancements to the Montgomery Multiplication and also to Square & Multiply algorithm. Bit Forwarding 1-bit (BFW1) algorithm has been implemented to evaluate modular exponentiation that resulted in 11.11% improvement in throughput, and 1.90% reduction in power consumption. A Dual-core RSA processor with a hardware scheduler has been designed for performing concurrent cryptographic transformations to attain better throughput without increasing the frequency. The proposed hardware scheduler is able to increase the throughput of 95.85% for MSM algorithm and 117.61% for BFW1 for 1024-bit key with reference to the MME42_C2 algorithm. The results have been verified for a key of length 1024-bits, up to 32-cores. This is scalable, by proportionally increasing BRAM and priority queue size.