Design of Reconfigurable FRM Channelizer using Resource Shared Non-maximally Decimated Masking Filters

Abstract

This paper presents a reconfigurable frequency response masking (FRM) wideband channelizer architecture which is characterized by low computational and hardware complexity. The proposed hardware efficient architecture is realized by incorporating resource shared non-maximally decimated filter bank in the implementation of the FRM wideband channelizer structure. The coefficients of the proposed architecture are optimized and made multiplier-free using Pareto based meta-heuristic algorithm in the canonic signed digit (CSD) space for reducing the total power consumption of the architecture. The architecture is finally designed and synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with existing channnelizer architectures. The comparison highlights the advantages of the proposed architecture in terms of hardware complexity, power and workload in realizing sharp wideband channel filters.