Abstract

This chapter presents the hardware realization of Neural Processing Element (NPE). The NPE executes the well-known nonlinear threshold function of the weighted summation, and behaves as an artificial neuron in an artificial neural network. The synaptic weighting and summing using pulse coded Modified Neural-Type Cells (MNTC) are presented. The basic information processing is in the form pulse duty cycle modulation. A prototype CMOS chip with 2µm minimum feature size was designed and measurements on the fabricated chip are included.

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