Design of power optimized memory circuit using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array

Abstract

In this work, we designed a power efficient memory circuit using family of various HSTL IO Standards on 28nm Field Programmable Gate Array (FPGA). Nine different HSTL IO Standards are compared with each other to search the most power efficient one. We validated our circuit with different HSTL IO Standards and on Different frequency range to obtain a most power efficient circuit. In our experiment, there is 87.44% power reduction when HSTL_I is replaced with HSTL_I_DCI_18 on 1 GHz frequency and 76.32% power reduction where we use HSTL_I_12 at place of HSTL_I_DCI_12. According to this experiment, HSTL_I is proved a best energy efficient IO Standard when compared with any other family of HSTL. To design this energy efficient memory circuit we are using Verilog as HDL, Xilinx ISE14.6 simulator with kintex-7 FPGA.