Design of PFD with free dead zone and minimized blind zone for high speed PLL application

Abstract

ABSTRACT In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 − 4 operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 in the phase characteristics which improves the output phase noise as −132.9 at 1 offset frequency. The power consumption is minimised upto 417.3 @ 4 operating frequency. The design is simulated in standard 0.18 CMOS technology node with 1.8 power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication.