Abstract
Two design flows of the Petri net-based cyber-physical systems oriented towards implementation in an FPGA are presented in the paper. The first method is based on the behavioural description of the system. The control part of the cyber-physical system is specified by an interpreted Petri net, and is described directly in the synthesisable Verilog hardware language for further implementation in the programmable device. The second technique involves splitting the design into sequential modules. In particular, adequate decomposition and synchronisation algorithms are proposed. The resulting modules are further modelled within the Verilog language as the composition of sequential automata. The presented design flows are supported by theoretical background, and templates of Verilog codes. The proposed techniques are illustrated by a real-life example of a multi-robot cyber-physical system, where each step of the proposed flows is explained in detail, including modelling, description of the system in the Verilog language, and final implementation within the FPGA device. The results obtained during the verification and validation confirm the proper functionality of the system designed by both design flows.
Highlights
A cyber-physical system (CPS) integrates computational aspects with physical processes [1,2,3]
This paper is focused on the design methods of the control part of cyber-physical systems specified by a Petri net and oriented towards implementation in the field programmable gate array (FPGA) device
This paper proposes two design flows for the control part of a cyber-physical system intended for implementation in the FPGA device
Summary
A cyber-physical system (CPS) integrates computational aspects with physical processes [1,2,3]. The main advantage of the Petri net-based design is the possibility of the graphical specification of a system [17,18,19,20] This paper is focused on the design methods of the control part of cyber-physical systems specified by a Petri net and oriented towards implementation in the FPGA device. The main aim of the presented techniques is to address the lack of strict and clear design flows of the Petri net-based models oriented towards further implementation in an FPGA.
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