Design of optimum power, delay efficient level shifter for biomedical applications

Abstract

The need for low power and less delay CMOS technology has led to the emergence of multi-voltage domains for biomedical applications. So to interface with these domains, a level shifter forms an essential component. Also a level shifter reduces the crowbar current that arises due to different voltage domains. This paper focusses on less delay and an optimum power dissipated level shifter which has additional keeper transistors compared to an earlier proposed level shifter. The keeper transistors reduce the delay in the regeneration latch by switching ON the corresponding PMOS transistors whenever the output node is low. Thus the proposed level shifter could efficiently convert from 1.1V to 1.8V with an optimum power dissipation of 33.52ps and a delay of 103.68ps for a supply voltage of 1.8V. Also, it could tolerate supply voltages of 18V and provide a shift from 3V to 18V efficiently. The simulations are done under 180nm CMOS technology tool in the Mentor Graphics.