Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking

Abstract

This paper discusses design of on-chip multi-layered inductor. On-chip inductor is an important component for ana-log/RF ICs. In on-chip inductor design, there are many structural parameters and we have to consider not only the inductance value but also the parasitics and the area. Thus, the design strategy is not clear yet. We prepare a large dataset of on-chip inductors by a static field-solver and analyze the dataset by principle component analysis (PCA). PCA shows that the characteristics can be described by two components even in the 4-dimensional space of the resistance, the inductance, the capacitance, and the area. According to the dimension reduction, we can guess the relationship between R, L, C and the area from a few samples.