Abstract
As scaling of technology decreases and reduces the feature size leads to an increase in the number of Intellectual Property cores and functional blocks in a System on Chip. A Network on Chip (NoC) is the new paradigm to handle overheads of intercommunication among Processing Elements (PEs). A typical switch consists of a total of five I/O ports, including four directional ports and one local port for efficient data transfer between the source PE and destination PE. The structure of the crossbar switch is realized with Code Division Multiple Access recently. Routing algorithm defined that the way data how transferred from the source to destination through intermediate routers. The scheduling algorithm resolves the arbitration among the ports in NoC router.
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