Abstract

The use of quantum-dot cellular automata (QCA) technology for the design of logic circuits has shown to increase data transfer rates up to 2 THz. In QCA technology, circuits are designed to have an ultra-small feature size as well as ultra-low power consumption. Grain-128 is one of the best stream ciphers in the final list of the eSTREAM project. In this paper, we have designed and simulated the main blocks of this algorithm including XOR gate, linear-feedback shift register (LFSR) and nonlinear-feedback shift register (NLFSR) using QCA technology. The designs of these blocks using the QCA Designer simulator are given and the main factors such as area, complexity and delay are estimated. Furthermore, ModelSim software is used to simulate HDLQ model of the QCA Grain-128 stream cipher algorithm. The results indicate that the main parameters of the proposed Grain-128, such as area and throughput, are improved as well.

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