Abstract

The neuron MOS transistor (neuMOS) is a new device with multi-input gates and one floating gate. It is capable of obtaining a weighted sum calculation of multi-input gates signals and then operating the threshold based on the result of summation, thereby simulating the function of biological neurons. The neuron MOS transistor' characteristics about multiple input gates and the floating gate capacitance coupling effect can be used to solve the output multi-valued problem. Through studying the design principles of multi-valued logic circuit and the redundant suppression method, this paper presents a design scheme of multi-valued double-edge-triggered JK flip-flop. Compared with the conventional multi-valued JK flip-flop, this circuit has the characteristic of reduction the redundant leap of clock, low power consumption and fast speed etc. Furthermore, the proposed scheme in this paper can be further apply to design higher radix multi-valued circuits. Finally, the above designed circuit is verified by PSPICE simulation.1

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