Design of Multi-time Programmable Memory for PMICs

Abstract

In this paper, a multi-time programmable (MTP) cell based on a 0.18 μm bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.