Design of multithreaded coprocessor IP core for embedded SoC chip

Abstract

Increasing demand for high performance has impelled the development of process technology and IC design technology. Due to production technology restrictions, traditional single-core processors have encountered bottlenecks both in frequency and performance. Heterogeneous multi-core SoC, such as CPU + coprocessor + peripherals, is accepted as a cost-effective solution for the increasing computation demands in embedded system. The system performance depends on the processor frequency, the memory access rate, and the I/O access rate, but their development is unbalanced, and CPU has to wait for the response from the memory or I/O for a long time in order to continue processing. Hardware multithreading technology has been used to effectively hide memory latency and significantly increase total system performance with low cost. This paper presents a design of coprocessor IP based on altera PicaRISC multithreaded processor which can execute eight threads simultaneously using a time-slicing multithreading approach. The IP core was designed based on avalon bus, and can be easily integrated into nearly any system. The test result shows that fft3780 calculation can speed up to 9 times using 16 threads.