Design of Multioctave High-Efficiency Power Amplifiers Using Stochastic Reduced Order Models

Abstract

This paper presents a novel general design method of frequency varying impedance matching. The method is applied to design of a broadband high-efficiency power amplifier (PA). The proposed method defines the optimal impedance regions of a PA at several frequency sections over the operational frequency band. These regions contain the impedances that can achieve a high output power and a high-power added efficiency (PAE) simultaneously. A low-pass $LC$ -ladder circuit is selected as the matching network (MN). The element values of the MN can be obtained using a synthesizing method based on stochastic reduced order models and Voronoi partition. The MN provides desired impedance in the predefined optimal impedance region at each frequency section. Thus, optimal output power and PAE of the PA can be achieved. To validate the proposed method, two eighth-order low-pass $LC$ -ladder networks are designed as the input and output MNs, respectively. A gallium nitride (GaN) HEMT from Cree is employed as the active device. Packaging parasitic of the transistor has been taken into account. A PA is designed, fabricated, and measured. The measurement results show that the PA can achieve P1 dB PAE of better than 60% over a fractional bandwidth of 160% (0.2–1.8 GHz). The output power is 42–45 dBm (16–32 W), and the gain is 12–15 dB. The performance of the PA outperforms existing broadband high-efficiency PAs in many aspects, which demonstrates the excellence of the proposed method.