Design of Multihop Communication Systems Under Hardware Manufacturing Defects and Self Interference

Abstract

Most studies on multi-hop communication systems are actually based on the assumption that hardware parts are built with high quality transmit/receive radio frequency chains, which are expensive and power-hungry. In practice, low cost hardware components are employed, which are prone to hardware manufacturing defects (e.g., phase noise, nonlinear power amplifier, inphase/quadrature imbalance, nonlinear low noise amplifier and analog to digital converter impairments). This paper focuses on the design of the transmitter, relay stations (RSs) and receiver for multi-hop communication systems under hardware defects. This paper analyzes the hardware defects and their impacts on the performance of multi-hop communication system. In addition, the impact of self-interference at the RSs is considered. The effect of hardware defects is modeled using distortion noises. A closed-form expression for the signal to noise and distortion ratios (SNDRs) is mathematically derived, then the performance metrics (i.e., SNDR, outage probability (OP) and ergodic capacity) are calculated, accounting for hardware defects. In addition, exact form expression of the average bit error probability is derived. To facilitate comparison, performance metrics of the proposed multi-hop relaying system and ideal system are illustrated. We also propose a linear minimum mean square error (LMMSE) and self-interference cancellation technique to mitigate the hardware defects. The results reveal that hardware defects can degrade the system performance. In addition, SNDR ceiling is inversely proportional to the summation of the square of hardware defect lev el. Also, the proposed mitigation technique can enhance the system performance.