Design of M-tree Adder using majority logic for removal of artifacts in bio signal

Abstract

This research's motivation has focused on signal processing in VLSI design for improving the system throughput in terms of high performance, energy-efficient, high speed, and small chip area. Very Large Scale Integrated circuit plays a vital role in modern technologies. The technology improvements happened because a general digital system design's processing device faces ethical challenges for intricate circuit design. In the recent era, the VLSI has the most compact and powerful IC fabrication technique to improve an individual processor's efficiency. This chapter stretches the design of digital circuits such as binary adders, multipliers, and implementation of FIR in signal processing, which is associated with a novel algorithm for the removal of power line interference in the bio-signal application. Also, deal with the current trends to identify the various pipeline architecture design and algorithms to bring out an optimized solution using a modern analytical method to improve the processor speed and accuracy. The proposed adder has achieved 96% efficiency in terms of gate count, delay, and power compared with existing analysis. Digital system design produces 83.5% efficiency in an existing system and it required the maximum number of gate count and an increasing number of delays when compared with recent research. The design summary is analyzed by using XILINX 14.7 ISE synthesis and the implementation process is highly reached with the help of MATLAB 2018a. IC fabrication is the most important design process in today's VLSI manufacturing industry. Application of SOC is used to fabricate more chips with the help of silicon resonator, to accomplish the circuit complexity by using silicon resonator which is more suitable for the fabrication process and reducing manufacturing cost.