Design of Median Filtering System Based on FPGA for Large Windows

Abstract

Aiming at the problem of high denoising performance and fast processing speed in the digital image noise suppression process, based on the conventional median filtering algorithm, a scheme for implementing a $5\times 5$ fast median filter using the merged insertion sorting algorithm is proposed. Reduced the number of times to obtain the median value and improve the image processing speed. The algorithm's hardware design was successfully completed in Altera's Quartus II software development environment. Compared with conventional algorithms, the scheme is simple and easy to operate, fast in calculation speed, and can meet the requirements of real-time performance. It is easy to implement on FPGA and provides eliable technical support for the field of image denoising with high real-time requirements.