Abstract
This paper describes a low power dissipation super high speed 1:16 demultiplexer using SMIC 0.18μm CMOS (Complementary Metal Oxide Semiconductor) RF process. The tree-type structure is adopted. Single-ended dynamic load latch is proposed for high speed 1:2 demultiplexer cell while CMOS quasi-static flip flop for medium speed 1:2 demultiplexer cell and dynamic CMOS logic for low speed 1:2 demultiplexer. The concrete circuits are composed of latches, frequency dividers and I/O buffers. Output data rate is up to 10-Gb/s. The total power consumption of the chip is about 100mW at a supply voltage of 1.2V.
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