Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops

Lamjed Touil,Abdelaziz Hamdi,Ismail Gassoumi,Abdellatif Mtibaa

doi:10.1155/2020/8108591

Abstract

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

Highlights

Power consumption presents an important issue when designing electronic devices such as mobile phones
The finite impulse response (FIR) filter is widely used as a critical component for implementing several digital signal processing (DSP) hardware circuits for their guaranteed linear phase and stability. ese circuits perform key operations in various recent mobile computing and portable multimedia applications such as high-efficiency video coding (HEVC), channel equalization, speech processing, and software defined radio (SDR)
We propose a combination of (MBFFs) and (DDCG) techniques on a single algorithm applied to an appropriate structure of the FIR filter for power saving

Summary

Introduction

Power consumption presents an important issue when designing electronic devices such as mobile phones. The finite impulse response (FIR) filter is widely used as a critical component for implementing several digital signal processing (DSP) hardware circuits for their guaranteed linear phase and stability. Is fact pushed designers to search for new methods to grant low power consumption for the FIR filter. In several applications, such as the SDR channelizer, there is a need to implement the FIR filters in reconfigurable hardware [1, 2]. In [3, 4], authors have minimized power consumption of the FIR filter by reducing the filter coefficients without modifying its order. In [13], the data-driven clock gating (DDCG) technique has been used for power digital filter optimization. Several architectures have been proposed in the last recent years

Methods

Results

Conclusion