Design of Low Power Stacked Inverter Based SRAM Cell with Improved Write Ability

Abstract

This paper puts forth double ended low power static random access memory (SRAM) cell structure that uses low power stacked inverters to reduce the power dissipation. The power dissipation in static mode is further reduced by feeding the cross coupled inverters with lower supply voltage during hold mode along with power gating. Simulation results in the Cadence Virtuoso design environment using 65 nm technology library show a 47.8% saving in the total power dissipation, 20.14% saving in static power dissipation and 83% improvement in the energy delay product respectively, in contrast to the 6T regular SRAM cell. The stability analysis shows that the propounded SRAM cell has bigger write ability as opposed to the basic 6T SRAM cell using the N-curve methodology.