Design of Low Power FFT using Self-sleep Buffer with Body bias Technique

Abstract

Leakage power has become an important contributing factor of power for the CMOS circuits in deep sub-micron process. MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode. Placing a global sleep device is not practical and sleep device at fine grain level involves more number of sleep transistors and more routing space. Distributed MTCMOS is better technique with self sleep circuit to avoid complexities in routing and sleep distribution network. A simple FFT processor is designed with self sleep buffer using body bias to reduce its standby power. Ccomparisons are made between leakage power for FFT implemented in CMOS and distributed self sleep FFT using the 90nm CMOS technology in cadence tools.