Design of Low Power CMOS Based Schmitt Trigger in 180nm Technology

Abstract

In this paper, CMOS based Schmitt Trigger circuits have been considered using the one pMOS two layer feedback approach and an nMOS only Schmitt Trigger with voltage enhancer procedure. Schmitt Trigger is a vital circuit used in obtaining the digitized output of an input signal. The paper explores the design and scrutiny of low power techniques. The simulations have been carried out in SPICE based on TSMC 180nm CMOS technology. Conventional Schmitt Trigger by means of the primary CMOS inverters is used as reference circuit. Evaluation of power dissipation of the circuit is carried out. The conventional model had the power dissipation of 123.07p W with a supply voltage of 1.8V. The proposed circuit which was made by using the one pMOS two layer feedback technique had the power dissipation of 112.72pW while the proposed circuit using nMOS only pull up network with a voltage enhancer showed a power dissipation of 71.45pW which gave 41.94% reduction in power consumption as compared to the conventional circuit. The study gives us a perception about the performance of the circuit when exposed to various approaches, in so doing refining specific characteristics of the circuit.