Abstract
In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.
Highlights
In today’s VLSI circuit designs, there is a significant increase in the power consumption due to the increasing speed and complexity of the circuits
Delay, and power consumption, the various adders are categorized as ripple carry adder (RCA), carry select adder (CSLA), and carry lookahead adder (CLAA)
The power consumption and delay time of proposed 8-bit CSLA are calculated for all input conditions and the worst case power consumption as well as delay time is noted down
Summary
In today’s VLSI circuit designs, there is a significant increase in the power consumption due to the increasing speed and complexity of the circuits. As the demand for portable equipment like laptops and cellular phones is increasing rapidly, great attention has been focused on power efficient circuit designs [1,2,3,4]. Adders are the basic building blocks of the complex arithmetic circuits. Having adders with fast addition operation and low power along with low area consumption is still a challenging issue. Delay, and power consumption, the various adders are categorized as ripple carry adder (RCA), carry select adder (CSLA), and carry lookahead adder (CLAA). CSLA provides a compromise between the large area with small delay of CLAA and small area but longer delay of RCA [8]. Depending on the value of previous carry, the final sum and carry outputs are selected using multiplexer
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