Abstract
This study presents an architectural approach to the design of Low power and area efficient reconfigurable Finite Impulse Response (FIR) filter. FIR digital filters are used in DSP by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. The proposed architectures implemented by using carry save adder, it offer Low power and area reductions and compared to the best existing reconfigurable FIR filter implementations in the literature and the proposed architectures have been implemented and tested on Spartan-3 xc3s200-5pq208 Field-Programmable Gate Array (FPGA) and synthesized.
Highlights
The explosive growth in mobile computing and portable multimedia applications has increased the demand for low power Digital Signal Processing (DSP) systems
In Our proposed new reconfigurable Finite Impulse Response (FIR) filter, PSM multiplier with BCSE algorithm and shift and add method is used to multiplication computation
The results presented establish a clear area advantage of Proposed FIR architecture over prior architecture For Typical filter parameters with comparable Low power and Low area
Summary
The explosive growth in mobile computing and portable multimedia applications has increased the demand for low power Digital Signal Processing (DSP) systems. FIR filter structures are simplified to add and shift operations and minimizing the number of additions/subtractions is one of the main goals of the research. In Our proposed new reconfigurable FIR filter, PSM multiplier with BCSE algorithm and shift and add method is used to multiplication computation.
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