Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study

Abstract

In this paper a low power adiabatic SRAM cell is realized using DTGAL, CPAL and ACPL at 180 and 90 nm using SPICE. The proposed SRAM consists of storage cell, sense amplifier and read/write drivers. P-type adiabatic complementary pass transistor logic (P-ACPL) that is complementary to the N-ACPL is proposed and is used to drive write word lines and power the storage cells. The N-type adiabatic complementary pass transistor logic (N-ACPL) is used to drive read/write bit lines and read word lines. The power consumption of three SRAM circuits was observed for different frequencies up to 500 MHz. The SPICE simulation results show that ACPL is efficient technique both in terms of power consumption and area needed for the design. At 90 nm for 500 MHz, ACPL SRAM has power consumption of 51% and 17% lesser than DTGAL and CPAL SRAM's respectively; also ACPL needed 39% and 18% lesser area than DTGAL and CPAL for SRAM circuit.