Abstract
The paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized in a complementary architecture, which is usually preferred in low-power applications as it exploits ≈50% bias current reduction with double efficiency compared to the structure with single coupled, when operating in the current-limited regime. A stacked spiral inductor exhibiting a Q factor of 5.8, with pMOS based depletion mode varactor of 32% in tuning range, corresponding to 3.2-3.6GHz of tuning frequency, is implemented in 0.18µm CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1MHz of offset frequency is indicated to be -114.3dBc/Hz, while dissipating 11.0mW of core circuit power.
Highlights
Increasing demand for higher capacity in the growing LAN (WLAN) market has led to the introduction of a new generation of WLAN standards using more spectrally efficient modulation techniques
The 802.11a standards are based on orthogonal frequency division multiplexing (OFDM) modulation, where 52 uniformly spaced carriers are independently modulated with PSK or QAM, requires circuit architecture with low amplitude, high linearity and low phase mismatch, improved Error Vector Magnitude (EVM) performance
The frequency planning scheme description for IEEE 802.11a application is followed by the review on the design of the stacked spiral inductor, subsequently by the utilized pMOS based capacitor and the description of the integrated complementary based source injection parallel coupled (SIPC)-quadrature voltage controlled oscillator (QVCO) architecture
Summary
Increasing demand for higher capacity in the growing LAN (WLAN) market has led to the introduction of a new generation of WLAN standards using more spectrally efficient modulation techniques. A stacked spiral inductor with comparable Q factor and self resonant frequency is designed [6] and integrated into the QVCO architecture to provide frequency tuning via the LC tank configuration.
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