Design of Low Hardware Complexity Filter Banks for Communications Systems Employing Folding Number System

Abstract

In this paper, a new architecture to compute 1-D Discrete Wavelet Transform (DWT) based on Folding Number System (FNS) is introduced. Numbers for FNS are extracted directly from analog input without any forward converter like in the Residue Number System (RNS) based DWT. The large Dynamic Range makes the FNS DWT more efficient than those implemented using RNS systems. The proposed 1D DWT architecture makes use of the relation between the coefficients of the low-pass and high-pass decomposition filters for orthogonal wavelets families to compute the transform with minimum numbers of modular multipliers. These multipliers are based on pipelined Look-Up Tables (LUT). A 6-tap Daubechies analysis filter bank is synthesized at a structural level using VHDL. FLEX10K devices of Altera are used in the simulation of DWT using binary arithmetic, RNS and FNS to evaluate its performance. Simulations show a significant throughput improvement is achieved in the proposed FNS DWT architecture when {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> - 1.2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> ,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> + 1} moduli set is used.