Design of JESD204B High Speed Interface for Waveform Digitization

Abstract

At present, due to the wide application of nuclear and particle physics experiments in the waveform digitization technology and the increasing demand of high speed and high accuracy for ADC, the PCB layout is more and more complex and the cost is higher. In order to simplify the design and reduce the cost, this paper put forward the scheme of JESD204B high speed interface for the waveform digitization technology in nuclear and particle physics experiments. Firstly the interface protocol and the demand of JESD204B is introduced. Then the solution based on Altera FPGA and special JESD204B clock chip LMK0482x is proposed. The preliminary test results show that the clock performance is excellent and JESD204B link is functioning normally. Moreover, the system has an excellent performance. The scheme can realize the design of JESD204B high speed interface and therefore be applied to the waveform digitization technology.