Design of Ion-Implanted Junction Termination Extension for Vertical GaN Pin Rectifiers

Abstract

Gallium-nitride and related materials have become suitable semiconductor platforms for next-generation power electronic devices. This materials system leverages unique properties of wider energy bandgap, higher carrier mobility, and ultrashort carrier recombination lifetime to achieve much improved bipolar switching characteristics when compared to Si- or SiC-based counterparts. In recent years, vertical GaN switches such as PIN rectifiers, junction barrier Schottky (JBS) diodes, and junction field-effect transistors (JFETs) have been actively sought in hopes to achieve low-loss device performance at kilo-volt (kV) operation range. Over the years, significant progresses in low-defect-density substrate preparation and high-quality epitaxial growth using metalorganic chemical vapor deposition (MOCVD) reactors, along with robust fabrication processing techniques helped achieve many impressive GaN-based power device demonstrations. As vertical GaN devices operate at the kV ranges, proper engineering of the electric field is a key to exploiting the ultimate device performance. To this end, several device-level design strategies such as field plates, beveled sidewalls, and junction termination extensions have been studied. In the context of realizing a planar device topology in GaN materials systems, ion implantation into GaN materials systems offer new opportunities to provide precise control of inhomogeneous carrier distribution for the creation of versatile doping profiles and geometries such as selectively doped regions or highly resistive regions at arbitrary locations in GaN devices.In this presentation, we will discuss a study of the floating guard rings (FGRs) designs that utilize a nitrogen-ion implantation isolation technique. The designs can effectively mitigate the electric field crowding effect and enable robust avalanching capability in vertical GaN PIN rectifiers. Using 1.2-kV GaN PIN rectifiers as design examples, a set of numerical simulation study was performed using a TCAD-Sentaurus software package. The results showed that a closely packed FGRs with a gap of adjacent FGRs in the range of 1-3 microns, a width of the FGRs in the range of 4 to 6 microns, along with a variable-width FGR design toward the outer rings can effectively suppress the peak electric field distribution at edge of the main junction and the surface of junction termination extensions. For example, consider a GaN PIN rectifier structure with a drift layer that consists of 6 microns of unintentionally doped (UID) GaN (n= 5×1015 cm-3) and a 4-micron-thick lightly doped GaN (n = 2×1016 cm-3). The FGR structures can be formed by creating highly resistive GaN regions in the epitaxially grown p-GaN layer using an ion implantation technique. In this design, five of the FGRs have 1-micron-wide undoped GaN and a 6-micron-wide p-GaN region in the p-GaN layer. The outermost FGR (the 6th FGR) is designed to have a 2-micron-wide undoped GaN and 5-micron-wide p-GaN extension. The resulting field distribution showed an effective suppression of the field crowding effect at the edge of the main junction (Figure 1(a)) and a smooth electric potential drop along the lateral direction can be achieved (Figure 1(b)). As shown in Figure 2, the electric field distribution at the vertical junction was plotted for two FGR designs with and without a metal plate on top of the p-GaN region. The electric field distribution of the main junction was also plotted for comparison. It is clearly shown that the peak electric field at the vertical junction is effectively reduced with the metal-plated FGRs by >10% when compared to a non-plated FGRs. Reduced peak electric field in typically high-electric-field regions can safeguard the device from experiencing premature breakdown for robust switching operations. We found that 6 FGRs with a total lateral extension of <45 microns from the main pn junction are sufficient to provide effective junction termination for 1.2 kV devices. Such designs could also support for devices with a blocking voltage up to 1.6 kV.FGR designs were implemented in GaN PIN rectifiers for experimental validation. The fabrication processing of vertical GaN PIN rectifiers was grown on n-type free-standing or bulk GaN substrates using a MOCVD reactor. The cathode was formed by depositing Ti/Al-based ohmic contact on the backside of the wafer, and the anode electrode was formed on the topside p-type GaN layer. Nitrogen-ion implantation was employed to create FGR structures and served as a mean of inter-device isolation. Detailed design strategies of the FGRs, device processing and device characterizations will be discussed in the conference. Figure 1