Abstract
Abstract Fast Fourier transform (FFT) has gained broader usage in the field of digital communication and various types of signal processing algorithms. In this paper, an attempt has been taken to design a modular-based CBNS addition–subtraction unit (CASU) involving complex binary number system (CBNS). The three basic modules (\(m_0\), \(m_1\), \(m_2\)) have been utilized to develop CASU for realization using the conceptual approach. A novel design technique involving the concepts of blocks and subblocks has been developed to limit input handling capability of modules in Kintex-7 family of Xilinx XC7K325T-2FFG900C FPGA. The CASU design has then been extended for development of CBNS complex-valued FFT (CFFT) processor by maintaining radix-2 DIT algorithm. The simulation of CBNS-CFFT has been done on Vivado Design Suite 2014.3. An effective performance comparison of CBNS-CFFT and normal binary number system (NBNS)-CFFT has been incorporated to highlight the supremacy of CBNS-CFFT in respect of silicon area, path delay, and memory utilization.KeywordsCBNSCASUConceptual approachCFFTBit shiftFPGA
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