Abstract
A design of broadband power amplifier (PA) which uses harmonic-optimised matching network (MN) is designed to maintain high efficiency. The load–pull data is used to construct the optimal impedance areas in fundamental and harmonic parts. Then, the modified simplified real frequency technique algorithm is employed to design output-MN through constructing the defined harmonic-error functions. A 10 W Cree gallium nitride high-electron-mobility transistor device CGH40010F is used to validate this method. The proposed PA has a 40% bandwidth (1.8–2.7 GHz) and a 64–81% drain efficiency. The digital pre-distortion process shows the adjacent channel leakage ratio (ACLR) is <−52 dBc at 2.25 GHz.
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