Design of high-speed fully serial tree multiplier

Abstract

The paper describes and compares three different designs for a high-speed two's-complement, fullyserial tree multiplier, the first of which uses a correction technique, the second Booth's algorithm, and the third employs sign extension. All three designs, each of which possess advantages for different applications, may be clocked at the ceiling frequency determined by the delay through an adder and a flip-flop. Each design was simulated functionally at the gate level, an exercise that revealed several shortcomings and redundancies in what had been considered to be an optimal design. The importance of simulation for design verification in such cases is stressed and a straightforward method for accomplishing it, based on a synchronousstate machine approach and using a general-purpose language (Pascal), is presented.