Design of High Sensitivity Radiofrequency Energy Harvesters Dedicated to Low-Power Applications

Abstract

The Radiofrequency (RF) energy harvesting is a widespread technique to extend the lifetime of devices in low power applications such as Wireless Sensor Networks (WSNs). This paper presents the comparison between a n-stage traditional CMOS voltage multiplier and a n-stage voltage multiplier using bulk biasing to overcome the threshold voltage drop. The two rectifiers operate at 900 MHz ISM band and are prototyped using a standard CMOS 130 nm process. The rectifier circuits were placed into a quad flat no leads (QFN) package and mounted on a standard FR4 board with commercially available devices. The bulk-biased rectifier achieves a significant increase in power efficiency and low voltage-drop. Loaded by a 400 kΩ resistor, typically 3.6 μW/1.2 V, the power efficiency reaches 58%, which is an improvement of about 50% compared with the traditional circuit. Concerning the RF energy harvesters, they are able to deliver an output voltage of 1 V at approximately 900 MHz requiring an available input power of –25.5 dBm and –23 dBm using the bulk-biased and traditional architectures, respectively. Furthermore, the harvesters operate at 3 meters delivering an output power of 1 μW when a power source radiates 19 and 20.5 dBm EIRP, for bulk-biased and traditional circuit, respectively.