Design of High Precision Radix-8 MAF Unit with Reduced Latency

Abstract

Signal processing and image processing applications require floating-point computation in digital circuit designs. The floating-point calculation is recommended in almost all digital design applications to improve the accuracy of results. Different mathematical operations use floating-point mathematical operations and can be used to perform calculations and different logical units. The proposed work sugestes a double-MAF unit that uses radix-8 for multiplication and uses a common addition block for addition and multiplication operations. Firstly, floating-point numbers are transformed into IEEE 754 format, next to both addition and multiplication calculations are achieved. Extracts the fractional part of a number and performs a calculation based on the exponential difference between the numbers. The proposed curriculum is designed with a parallel structure that first extracts the decimal and exponential values of the first unit and then performs multiplication and addition operations in the second block. At last, the output is made in the third block where normalization and zero detection are performed. The proposed approach is then compared to the baseline approach, which shows improvements in energy consumption and maximum common path delay. The results showed that the delay is reduced by about 57%.