Design of High Performance Parallel Multiplication using FPGA

Abstract

In the recent decade, decimal arithmetic has received a lot of attention. In existing research on decimal multiplication, latency and area are two key factors. In any case, today's computerized frameworks and DSP applications; energy/power utilization is a pivotal thought. For quick DSP, low power and high speed multipliers are required. Because of its regular structure and ease of design, the array multiplier is one of the fastest multipliers. To boost multiplier speed and improve power dissipation with the least amount of delay, adders and CMOS power gating based CLA are employed. In the paired number framework, the significant issue in number-crunching relates to convey. A higher rad-ix number framework, Quaternary Signed Digit (QSD), is utilized to perform number juggling tasks without convey.