Design of High-Performance InAs–Si Heterojunction 2D–2D Tunnel FETs With Lateral and Vertical Tunneling Paths

Abstract

Double-gate tunneling FETs (TFETs) exploiting the 2D density-of-state switch are studied. A full-band and atomistic quantum transport simulator based on the sp3d5s* tight-binding model is used to solve the quantum transport problem taking into account both lateral and vertical band-to-band tunneling paths. The tunneling paths are identified by means of the calculation of the electron and hole generation rates. They are computed with an in-house tool based on the Flietner imaginary dispersion and a non-local path band-to-band tunneling model. First, a InGaAs electron–hole bilayer TFET is investigated. It is found that the suppression of lateral tunneling components is crucial to obtain a steep slope in this device. On the other hand, the presence of both tunneling components can boost the ON-current of TFETs. The latter can be achieved by implementing an InAs–Si heterostructure as 2D–2D TFET. Such a combination offers a device solution with both steep subthermal subthreshold swing and high ON-current. In the best case of an extremely thin InAs–Si 2D–2D TFET, the minimal swing would be SS = 28 mV/decade and the ON-current would reach 240 $\mu \text{A}/\mu \text{m}$ .