Abstract
This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple operation modes i.e. coarse, fine, and retention for high efficiency and transient enhancement. The proposed hybrid DF-LDO uses arrays of PMOS transistors in coarse and fine mode whereas in retention mode, only one comparator and NMOS are active and digital controller goes into the sleep mode. This results in the reduction of the power consumption and improves the output voltage ripples. In the retention mode, minimum number of blocks operate that reduces the current consumption as compared to coarse and fine modes. To further reduce the current consumption, the comparator with hysteresis is used. The proposed circuit is designed using CMOS 55 nm process. The input voltage range is from 0.8 ~ 1.5 V and the measured output voltage range is 0.756 ~ 1.456 V. The measured line regulation is 6 mV / V, and the regulation starts when the input voltage is 0.8 V. The measured load regulation is 2.3 mV/mA for maximum load current of 5 mA. The peak current efficiency of the proposed DF-LDO is 99.996 % with a maximum output voltage ripples value of 1.9 mV. The proposed digital LDO regulator active chip area is 0.012 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Highlights
The recent rapid growth of portable electronic devices such as battery-powered smartphones, laptops, and Bluetooth earphones requires the integration of circuits that require many functions in a limited area and low quiescent current
In the line with this trend, the CMOS process is gradually developed as a deep submicron process, and the supply voltage of analog circuits is lowered below 1V, and the LDO that supplies the voltage has a sub-threshold dropout voltage for maximum efficiency [6]-[8]
A lot of research have been carried out to address this major challenge as digital LDOs can usually deliver optimal output voltage under low power condition’s, such as near threshold voltage (NTV) levels
Summary
The recent rapid growth of portable electronic devices such as battery-powered smartphones, laptops, and Bluetooth earphones requires the integration of circuits that require many functions in a limited area and low quiescent current. Need conventional analog LDOs to consume more current when the input voltage is lowered, which makes it difficult to catch the bias voltage and uses a large power transistor to supply voltage to a block that consumes large currents [9], [10]. In this regard, the design of digital LDO is necessary and has many advantages over analog LDO. Digital LDOs do not require compensation conditions and stability unlike analog LDOs [13]
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