Design of High Gain CMOS Comparator with Slew Rate Of 10V/µS

Abstract

In present days mixed signal design is very important in many of system applications like Analog to digital convertors, switching circuits and communication blocks. In ADC architecture comparator is the main functional block. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input is greater or smaller than applied references. Settling time is important in analog signal processing in order to avoid the errors in the accuracy of processing analog signal and to have fast settling time. To get the fast settling time the circuit must be with high slew rate. A longer settling time implies that the rate of processing analog signals must be reduced. In this paper presented design of CMOS comparator of high gain in order of 10 with slew rate of 10v/μs. This architecture is operates at 3V power supply and design is simulated using LT-SPICE tool. Transient response, ac analysis and slew rate results also shown and discussed in this paper.