Design of high data rate, passive, far-field RFID tags in CMOS technology

Abstract

Radio frequency identification (RFID) is an exciting, rapidly growing, multi-disciplinary field with emerging technologies and applications. Today RFID is a generic term for technologies that use radio frequencies to automatically identify people or objects. In a typical RFID system, digital information is transferred between a base station and movable objects, using wireless communication techniques. The base station, called reader, is usually a complex device connected to a host computer or network. The movable objects are simple, inexpensive devices called tags, which are attached to people or objects to identify. In far-field RFID, coupling mechanism between reader and tag is based on propagation of electromagnetic waves. Passive, far-field tags don't contain a power source, but rely on wireless power transmission instead; they are powered by rectification of radio signal sent by reader. These tags send data to reader by changing load connected to their antenna in a coded manner, a technique known as backscatter modulation. As of today (2009), passive RFID tags that are commercially available are typically optimized for operating at a large distance from reader. This inevitably comes at cost of a low data transfer rate. A new field in RFID is currently emerging, which focuses more on data rate than on operating range. The development of such high data rate RFID tags, communicating at several megabit per second (Mbps), opens way to a variety of promising applications in areas of ambient intelligence and the internet of things. A typical example is wireless memory tag, which consists in a passive, far-field RFID tag containing high capacity, high speed nonvolatile memory. Such tags enable to store multimedia content (video, music...) that can be downloaded by user in a few seconds. In near future, this will probably become a popular new distribution method for various digital products. Designing such tags involves a number of challenges. Because they communicate at high data rate, they consume a significant amount of power. Particular care must be taken in order to optimize efficiency of wireless power transmission, so that tags can reach a decent operating range. This thesis work discusses how various tag building blocks, such as antenna and rectifier, impact efficiency. The principle of wireless voltage regulation is introduced. It allows to further improve efficiency by lowering losses not only in tag, but also in reader. Various experimental results are provided, which show amongst other things that power emitted by reader can be reduced at least by a factor of four. Realizing passive, far-field tags that can transfer information at high data rate with backscatter modulation is not a trivial task. This work aims to determine how to maximize useful backscattered power, which conveys information. Because reader has a finite sensitivity, it needs to receive a minimum backscattered power to recover data, which limits tag operating range. This research project brings to light a fundamental limitation concerning reader sensitivity, and proposes a model to estimate maximum tag reading range. In order to be widely accepted by market, an important characteristic of these tags is that they must be very inexpensive. Hence, tag's integrated circuit (IC) can't be realized using high performance, but costly, fabrication processes. For this reason, this research project focuses on tag ICs realized in a mainstream CMOS process, which implies specific challenges. In particular, impact on architecture and power efficiency of rectifier is discussed. There are basically two approaches to design high data rate, passive, far-field RFID tags. The first one is to base design on a single frequency architecture, and to use a unique carrier frequency for both wireless power transmission and communication. The other approach is use a dedicated carrier frequency for each of these two links, which leads to dual frequency architecture. This thesis work presents a practical design example for each of these architectures, including various experimental results. Both tag ICs are realized using UMC CMOS 0.18 µm technology. When reader emits 3.3 W effective isotropically radiated power (EIRP) at 866.6 MHz, and 10 mW EIRP at 2.44 GHz, dual frequency tag can be read at 10 Mbps at an operating range of 33 cm. The tag's rectifier reaches a power efficiency of 36%. As of today, this tag outperforms commercial products and published works in area of high data rate, passive transponders.