Design of High Accuracy, Power Efficient and Area Efficient 16x16 Approximate Multiplier

Abstract

Approximate Arithmetic has a great potential to design digital systems that consume less power and area without compromising delay. This technique is mainly utilized to design systems used in error tolerant Digital Signal Processing (DSP) applications as it simplifies the conventional circuit using certain approximation design strategy sacrificing the accuracy of the output. In this paper, a power and area efficient multipliers are proposed using approximate half adders, full adders and OR gates for partial product accumulation. OR gates are used in the Lower Significant Bit positions (LSB) and the approximate adders are used in Most Significant Bit (MSB) positions. This reduces the carry propagation for LSB bit positions. Initially, approximate half and full adders are proposed and using that an approximate unsigned and signed 4x4 multipliers design is shown. Accurate Wallace Tree multipliers (WTM) are also designed in order to determine the performance of the proposed approximate multipliers. The design of 8x8 and 16x16 unsigned and signed multipliers are proposed using OR gates and previously designed approximate multipliers. The designs are synthesized using Xilinx ISE using Basys 3 board at 100 MHz clock frequency. The proposed 16x16 unsigned multiplier reduces utilization and power by 35.67% and 36.45% when compared with unsigned 16x16 accurate Wallace Tree multiplier. The proposed 16x16 signed multiplier reduces utilization and power by 33.97% and 32.29% when compared with signed 16x16 accurate multiplier.